1. Field of the Invention
This invention relates to multipliers and multiplication methods capable of multiplying large multiplicands and performing multiple parallel multiplications of small multiplicands.
2. Description of Related Art
A multiplier is often one of the largest circuit units in a microprocessor or a digital signal processor (DSP). The size of a multiplier can be a particular problem in video processing where high-performance processing often requires parallel multiplications, Additionally, video processing often needs to multiply relatively small multiplicands (e.g., 8-bit time domain pixel data) and larger multiplicands (e.g., 16-bit frequency domain data.) A large multiplier designed for the larger multiplicands can multiply a pair of the smaller multiplicands, but providing a large number of large multipliers requires a large amount of circuit area and increases the manufacturing cost of an integrated circuit containing on-chip multipliers. Having two sets of multipliers, one set including a large number of smaller multipliers for small multiplicands and a second set containing a smaller number of larger multipliers for larger multiplicands, also requires a large circuit area without a corresponding increase in performance since the smaller multipliers generally cannot be used when multiplying larger multiplicands.
A processor or multiplier architecture is desired that requires a minimum circuit area, can multiply larger multiplicands, and perform multiple parallel multiplications of small multiplicands.